Description: 显卡中关于3D图形处理的源码，是VHDL版本的
喜欢硬件FPGA图像处理的可以看看，挺有意思-Graphics 3D graphics on the source, is like VHDL version of the FPGA hardware image processing can see quite interesting Platform: |
Size: 1686659 |
Author:dido wang |
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Description: 当按一次按健时，由于按健有反应时间、有抖动，可能你按一次机器感应到几次，防抖就是让在按键正常反应时间内机器只感应一次按键效果，防止误操作，本文是基于FPGA的按键防抖程序代码，用的是VHDL语言，内容包括原理，实际操作及源码等。-When you press a pressing health, because according to health have reaction time, jitter, you may press machine senses a few times, image stabilization in the key is to let the normal reaction time machine button only once induced effects, to prevent misuse, the paper is key FPGA-based image stabilization program code, using VHDL language, including theory, practice and source code, etc. Platform: |
Size: 293888 |
Author:李源码 |
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Description: 基于图像处理的中值滤波VHDL源码,能够实现对图像的滤波-Based on the median filter VHDL source image processing, image filtering can be achieved Platform: |
Size: 440320 |
Author:彭涛 |
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Description: vga
This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation.-This details a VGA controller component that handles VGA signal timing, written in VHDL for use with CPLDs and FPGAs. Figure 1 illustrates a typical example of the VGA controller integrated into a system. As shown, the VGA controller requires a pixel clock at the frequency of the VGA mode being implemented. It then derives all of the signal timing necessary to control the interface. It outputs the current pixel coordinates to allow an image source to provide the appropriate pixel values to the video DAC, which in turn drives the VGA monitor’s analog inputs. It also provides the sync signals for the VGA monitor. This component was designed using Quartus II, version 12.1. Resource requirements depend on the implementation. Platform: |
Size: 219136 |
Author:jiang nan |
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Description: 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese
的配套源码，基于quartus9.0用VHDL编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese
The matching source, based on quartus9.0 prepared using VHDL, the use of cyclone ii. Which includes FIR IIR FFT algorithm such as the realization of learning to image processing helpful. Platform: |
Size: 397312 |
Author:马博城 |
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Description: LFM pulse compression of the Matlab program, Including the final calculation of the compressed image peak signal to noise ratio and compression of the source, Achieve a grayscale image and further control for video surveillance. Platform: |
Size: 6144 |
Author:quipangang
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